The invention concerns a switched phase dual-modulus prescaler circuit having means for reducing power consumption. The dual-modulus prescaler or divider counter circuit forms part of a frequency synthesiser. Said circuit divides the frequency of at least a high frequency signal by a factor N in a first selected mode and by a factor N+M in a second selected mode. It includes several series connected dividers-by-two of the asynchronous type. One of these dividers-by-two is of the master-slave type for receiving two input signals in phase opposition and for supplying four signals phase shifted by 90xc2x0 in relation to each other. The circuit also includes a phase selector unit inserted between two of the dividers-by-two for receiving the four phased shifted signals of the first master-slave divider and for supplying one of the four phase shifted signals selected at the second divider. Two selection branches of the selector unit each receive two of the four phase shifted signals. A selection element of the selector unit is connected to each branch to provide at the output of said unit one of the four phase shifted signals selected in a division period determined as a function of the mode selected. For the selection of the phase-shifted signals, first control signals are provided by a control unit to the two branches, as well as to the selection element.
Frequency synthesisers are used particularly in wireless communication systems or, more generally, in telecommunication systems, in order to supply high frequency signals. The high frequency signals are likely to be used, for example, for demodulating RF signals received.
FIG. 1 shows an embodiment of a conventional frequency synthesiser with a dual-modulus prescaler circuit. This synthesiser includes first of all a reference oscillator, which is not shown. This oscillator supplies a frequency stable reference signal Fref to a phase and frequency detector 2. This detector also receives a divided frequency signal Fdiv from a dual-modulus prescaler circuit 5 in order to compare the reference signal and the divided frequency signal. As a function of the phase and frequency difference in signals Fref and Fdiv, the detector supplies a comparison signal to a low-pass filter 3 connected to a voltage controlled oscillator (VCO) 4. This voltage controlled oscillator receives a voltage control signal originating from the low-pass filter so that the oscillator generates at least a high frequency signal dependant on the comparison between signals Fref and Fdiv.
The voltage controlled oscillator can be a differential type oscillator so as to provide two high frequency signals Fs and Fsb in phase opposition to prescaler circuit 5 in a phase lock loop. At least one of high frequency signals Fs or Fsb can thus be used for demodulating operations in a radio-frequency signal receiver for example.
Dual-modulus prescaler circuit 5 has the power to allow frequency division by a division factor dependent on a selected mode. In order to do this, a logic circuit with two counters A and B is generally used to supply a mode selection to the prescaler circuit. This logic circuit 6, well known in this technical field, is controlled by a microprocessor and by divided frequency signal Fdiv. The two counters A and B are, in theory, clocked in synchronism by a same clock signal, but the number counted by each counter before zero reset is different. This thus allows logic circuit 6 to supply a mode signal to the prescaler circuit so as to change division mode in determined periods.
Several embodiments of dual-modulus type prescaler circuits have already been proposed, but since these circuits have to operate at high speed, they are more difficult to design than simple fixed division ratio frequency dividers. One of the difficulties is that, to obtain a frequency division in accordance with the first and second division factors, the logic part of the circuit slows down the whole circuit.
A conventional dual-modulus prescaler circuit, having to operate at high speed, includes a first synchronous division part, for the division factor selection, and a second asynchronous part. In general, the first synchronous division part is the only part operating at the highest frequency. This can be a drawback, since several flip-flops of the first division part are synchronised by the same signal, which is a high frequency signal, which involves high current consumption.
U.S. Pat. No. 6,067,339 discloses such a dual-modulus prescaler circuit. The circuit allows frequency division to be carried out in accordance with two division factors as a function of a selected mode. For example according to the mode selected, the factor can be equal to 64 or 65, or also to 128 or 130. This circuit includes several dividers-by-two, connected in series, of which one divider unit is synchronous to carry out a division by 4 or by 5, whereas the other dividers are of the asynchronous type.
This synchronous divider unit is arranged with a certain number of logic parts in order to allow the circuit to divide the high frequency signal by one of the two division factors that is selected. The unit includes two D type flip-flops clocked by the same clock signal which is an output signal of a first divider-by-two. However, one of the flip-flops of this unit is only used to obtain the division factor by 65 or by 130.
Usually, a synchronous divider unit of this type is intended to receive the high frequency signal directly. Thus, several flip-flops operate at high frequency, which is a drawback if one wishes to reduce the power consumption of such a prescaler circuit. One solution to this problem has been partially resolved by the circuit disclosed in U.S. Pat. No. 6,037,339, by placing a first divider-by-two of the asynchronous type before the synchronous divider unit. However, the first divider only divides the frequency of the high frequency signal by two, which means that the unit has to operate with a frequency that is still too high.
Another drawback with such a circuit arrangement is that the frequency division cannot be precisely adjusted in accordance with the two division factors, given that a first divider-by-two is particularly used for reducing the frequency of a high frequency signal. It is thus not possible to supply frequency divisions closer to each other.
In order to avoid the use of a synchronous divider unit, an embodiment of a dual-modulus prescaler circuit is presented in the article drafted by Messrs. Jan Craninckx and Michiel S. J. Steyaert, published in the IEEE integrated circuit journal, volume 31 of Jul. 7, 1996. This dual-modulus prescaler circuit includes only series connected dividers-by-two of the asynchronous type. This dual-modulus circuit thus includes a chain of seven asynchronous dividers-by-two interrupted by a phase selector unit to allow frequency division by 128 or 129. Only the first divider-by-two operates at the highest frequency, i.e. at the frequency of at least a received high frequency signal Fin.
A second divider-by-two of the master-slave type is connected to the first divider-by-two. This second master-slave divider is intended to supply four signals phase shifted by 90xc2x0 in relation to each other to the phase selector unit on the basis of two phase-opposition signals supplied by the first divider. With respect to the first of the four signals supplied by the master-slave divider, the other signals are thus phase shifted by 90xc2x0, 180xc2x0 and 270xc2x0. The selector unit includes two differential amplifiers for amplifying and selecting the four phase shifted signals, and selection means for supplying one of the four signals selected at output.
The selector unit is controlled by a logic control unit as a function of the mode selected. In a first selected mode, said circuit has to divide the frequency of the high frequency signals by a division factor equal to 128. In this case, for all the division periods, the selector unit selects only one of the four signals. In a second selected mode, said circuit has to divide the frequency of the high frequency signals by a division factor equal to 129. In order to obtain this factor, phase switching between two of the four phase shifted signals is carried out in the selector unit as a function of the control signals generated by the control unit. At each division period, phase switching between a first signal supplied by the second divider and a second signal in a phase delay of 90xc2x0 with respect to the first signal is thus carried out. For this purpose, the control unit is clocked by the output signal of the last divider-by-two to thus supply control signals to the phase selector unit for the phase switching at each division period.
In order to modify the state of the control unit as a function of a selected mode, a NAND type logic gate receives, on the one hand, the mode signal and the output signal from the last divider-by-two. When the mode signal has a value of 0, the variation in the output signal at the control unit has no effect. Conversely, when the mode signal has a value of 1, the output signal is inverted by the NAND gate in order to clock the control unit and allow the selector unit to carry out the signal phase switching.
One drawback of such an arrangement of the logic gate and the NAND gate is that the control part of the selector unit is no longer entirely of the synchronous type. Consequently, a logic signal switching delay can occur, which is not desired even if such a delay can allow drops in potential to be prevented during the signal phase switching at the output of the selector unit.
Another drawback of the solution disclosed in the article by Messrs. Craninckx and Steyaert is that the amplifiers of the selector unit consume a significant amount of current in order to amplify the relatively high frequency signals. Consequently, the essential purpose of the selector unit inserted between two dividers-by-two of the chain of dividers is not to reduce the power consumption of the circuit with respect to a conventional dual-modulus prescaler circuit.
The main object of the present invention is thus to overcome the drawbacks of the prior art by providing a high speed dual-modulus prescaler circuit having means for reducing the power consumption of said circuit.
The invention therefore concerns a dual-modulus prescaler circuit of the aforecited type, where in the selector unit includes switching means controlled by second control signals supplied by the control unit so as to disconnect the electric power supply of one of the selection branches during a period in which the other branch is selected for supplying one of the four phase shifted signals at the output of the selector unit.
One advantage of the dual-modulus prescaler circuit according to the invention is that the current of the selector unit can be greatly reduced without affecting the circuit speed and the stability of the signals during switching. The decrease in current consumed can be 50% in a first selected mode and from 20 to 30% in the second selected mode.
In the first selected mode, the frequency of the high frequency signals is divided by a factor N equal, for example, to 64. In the second selected mode, the frequency of the high frequency signals is divided by a factor of N+M equal, for example, to 64.5. Thus, in the first mode at each division period, one of the amplifying branches of the selector unit is electrically powered, whereas the other branch is disconnected from the electric power supply. Conversely, in the second selected mode, the amplifying branches are inversely or alternately powered and disconnected from the electric power supply at each division period. The disconnected branch normally has to be powered a time period preceding switching between the branches, which is why the saving in power consumption is only 20 to 30%.
Another advantage of the dual-modulus prescaler circuit according to the invention, is that it is possible to have division factors sufficiently close so that the frequency of the high frequency signals can be adjusted precisely in the phase lock loop of the frequency synthesiser.
Another advantage of the dual-modulus prescaler circuit according to the invention, is that the control unit is clocked synchronously by a clock signal corresponding to the output signal of the latter or the second to last divider-by-two of the chain of dividers. This clock signal is thus never interrupted to clock the operations in the control unit. Moreover, the control signals produced by said control unit are exempt of any disturbance and/or any delay. Each control signal, for the amplifiers of each branch, is stabilised before each change in signals to be selected by a selection element of the selector unit.
It should be noted that the use of dividers-by-two, in particular of the asynchronous type, in the chain of dividers, facilitates manufacture of said high speed dual-modulus prescaler circuit.